This invention relates to an insulated gate type field effect transistor and a method of fabricating the same.
It is a recent tendency to substitute a MOS transistor which is a representative one of the insulated gate type field effect transistors FET for a bipolar type transistor because the construction and the process steps of manufacturing the MOS transistor are simpler than those of the bipolar transistor. A typical construction of a prior art MOS (FET) transistor is shown in FIG. 1. The MOS (FET) transistor 10 shown in FIG. 1 comprises a P type silicon semiconductor substrate 12, for example, having a source region 13 and a drain region 14 which are formed by diffusing an N type impurity into the substrate. An insulating film 16 such as a film of SiO.sub.2 overlies the source and drain regions 13 and 14 and an area therebetween. Source and drain electrodes 17 and 18 are formed over source 13 and drain, respectively, and a gate electrode 19 is formed on the insulating film 16. A channel 20 is formed in the area of substrate 12 between source and drain regions 13 and 14.
As can be noted from FIG. 1, the source, drain and gate electrodes of the MOS transistor having a construction as above described lie in substantially the same plane so that in order to electrically isolate each of these electrodes it is necessary to separate them by about several .mu.m. However, as the spacing between respective electrodes is increased it is not only difficult to miniaturize the pattern but also the parasitic capacitance between the source and drain electrodes through the semiconductor substrate increases thereby rendering it difficult to operate the transistor at high frequencies. This defect is more objectionable as the output power of the transistor increases. Also the increase in the spacing between respective electrodes makes it extremely difficult to obtain high density MOS integrated circuits. Although the use of polycrystalline silicon for the gate electrode is advantageous from the standpoint of stabilizing the characteristics of the transistor, where the gate length increases the gate wiring resistance increases which causes unbalance of the current and deterioration of the high frequency characteristic of the transistor. Further, with the construction described above, contact holes and the electrodes for the source and drain could not be formed in self-aligning fashion so that the steps requiring utmost skill and complicated workmanship is required for forming a fine pattern, thus increasing the cost of the transistor.